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pcf85103c-2 256 8-bit cmos eeprom with i 2 c-bus interface rev. 01 09 may 2002 product data 1. description the pcf85103c-2 is a ?oating gate electrically erasable programmable read only memory (eeprom) with 2 kbits (256 8-bit) non-volatile storage. by using an internal redundant storage code, it is fault tolerant to single bit errors. this feature dramatically increases the reliability compared to conventional eeproms. power consumption is low due to the full cmos technology used. the programming voltage is generated on-chip, using a voltage multiplier. data bytes are received and transmitted via the serial i 2 c-bus. up to eight pcf85103c-2 devices may be connected to the i 2 c-bus. chip select is accomplished by three address inputs (a0, a1 and a2). the pcf85103c-2 is identical to pcf85102c-2 except for the ?xed i 2 c address, allowing up to eight pcf85102c-2 and eight pcf85103c-2 on the same i 2 c-bus. 2. features n low power cmos: u 2.0 ma maximum operating current u maximum standby current 10 m a (at 6.0 v), typical 4 m a n non-volatile storage of 2 kbits organized as 256 8-bit n single supply with full operation down to 2.5 v n on-chip voltage multiplier n serial input/output i 2 c-bus n write operations: u byte write mode u 8-byte page write mode (minimizes total write time per byte) n read operations: u sequential read u random read n internal timer for writing (no external components) n internal power-on reset n 0 to 100 khz clock frequency n high reliability by using a redundant storage code n endurance: 1,000,000 erase/write (e/w) cycles at t amb =22 c n 10 years non-volatile data retention time n pin compatible to: pcf8570, pcf8571, pcf8572, pca8581, pcf8582, and pcf85102
philips semiconductors pcf85103c-2 256 8-bit cmos eeprom with i 2 c-bus interface product data rev. 01 09 may 2002 2 of 20 9397 750 09646 ? koninklijke philips electronics n.v. 2002. all rights reserved. n esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115, and 1000 v cdm per jesd22-c101 n latch-up testing is done to jedec standard jesd78 which exceeds 100 ma n offered in dip8 and so8 packages. 3. quick reference data 4. ordering information table 1: quick reference data symbol parameter conditions min typ max unit v dd supply voltage 2.5 - 6.0 v i ddr supply current read f scl = 100 khz v dd = 2.5 v - - 60 m a v dd =6v - - 200 m a i ddw supply current e/w f scl = 100 khz v dd = 2.5 v - - 0.6 ma v dd = 6 v - - 2.0 ma i dd(stb) standby supply current v dd = 2.5 v - - 3.5 m a v dd =6v - - 10 m a table 2: ordering information type number package north america name description version pcf85103c-2p pcf85103c2n dip8 plastic dual in-line package; 8 leads (300 mil) sot97-1 pcf85103c-2t pcf85103c2d so8 plastic small outline package 8 leads (straight); body width 3.9 mm sot96-1
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x philips semiconductors pcf85103c-2 256 8-bit cmos eeprom with i 2 c-bus interface 9397 750 09646 ? koninklijke philips electronics n.v. 2002. all rights reserved. product data rev. 01 09 may 2002 3 of 20 5. block diagram fig 1. block diagram. 002aaa250 test mode decoder power-on-reset i 2 c-bus control logic sequencer address high register byte counter divider ( 128) ee control timer ( 16) eeprom address pointer byte latch (8 bytes) shift register address switch input filter oscillator 8 4 3 n pcf85103c-2 4 v ss a1 a2 a0 3 2 1 8 v dd 6 5 scl sda
philips semiconductors pcf85103c-2 256 8-bit cmos eeprom with i 2 c-bus interface product data rev. 01 09 may 2002 4 of 20 9397 750 09646 ? koninklijke philips electronics n.v. 2002. all rights reserved. 6. pinning information 6.1 pinning 6.2 pin description 7. device addressing [1] the most signi?cant bit (msb) b7 is sent ?rst. a2, a1, a0 are hardware selectable pins. a system could have up to eight pcf85103c-2 devices on the same i 2 c-bus, equivalent to a 16 kbit eeprom or 8 pages of 256 bytes of memory. the eight addresses are de?ned by the state of the a0, a1, a2 inputs (logic level 1 when connected to v dd , logic level 0 when connected to gnd). figure 3 shows the various address combinations. fig 2. pin con?guration. 1 2 3 4 8 7 6 5 a0 a1 a2 v ss sda scl n.c. v dd pcf85103c-2 002aaa251 table 3: pin description symbol pin description a0 1 address input 0 a1 2 address input 1 a2 3 address input 2 v ss 4 negative supply voltage sda 5 serial data input/output (i 2 c-bus) scl 6 serial clock input (i 2 c-bus) n.c. 7 no connect v dd 8 positive supply voltage table 4: device address code selection device code chip enable r/ w bit b7 [1] b6 b5 b4 b3 b2 b1 b0 device 0 0 1 0 a2 a1 a0 r/ w
philips semiconductors pcf85103c-2 256 8-bit cmos eeprom with i 2 c-bus interface product data rev. 01 09 may 2002 5 of 20 9397 750 09646 ? koninklijke philips electronics n.v. 2002. all rights reserved. fig 3. device addressing. 002aaa252 256-byte page pcf85103c-2 device 1 256-byte page pcf85103c-2 device 2 256-byte page pcf85103c-2 device 3 256-byte page pcf85103c-2 device 4 256-byte page pcf85103c-2 device 5 256-byte page pcf85103c-2 device 6 256-byte page pcf85103c-2 device 7 256-byte page pcf85103c-2 device 8 i 2 c-bus a2 0 0 0 0 1 1 1 1 a1 0 0 1 1 0 0 1 1 a0 0 1 0 1 0 1 0 1
philips semiconductors pcf85103c-2 256 8-bit cmos eeprom with i 2 c-bus interface product data rev. 01 09 may 2002 6 of 20 9397 750 09646 ? koninklijke philips electronics n.v. 2002. all rights reserved. 8. functional description 8.1 i 2 c-bus protocol the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the serial bus consists of two bidirectional lines; one for data signals (sda), and one for clock signals (scl). both the sda and scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been de?ned: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control signals. 8.1.1 bus conditions the following bus conditions have been de?ned: bus not busy both data and clock lines remain high. start data transfer a change in the state of the data line, from high-to-low, while the clock is high, de?nes the start condition. stop data transfer a change in the state of the data line, from low-to-high, while the clock is high, de?nes the stop condition. data valid the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. there is one clock pulse per bit of data. 8.1.2 data transfer each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes, transferred between the start and stop conditions is limited to 7 bytes in the e/w mode and 8 bytes in the page e/w mode. data transfer is unlimited in the read mode. the information is transmitted in bytes and each receiver acknowledges with a ninth bit. within the i 2 c-bus speci?cations, a high-speed mode (100 khz clock rate) and a fast speed mode (400 khz clock rate) are de?ned. the pcf85103c-2 operates in only the high-speed mode. by de?nition, a device that sends a signal is called a transmitter, and the device which receives the signal is called a receiver. the device which controls the signal is called the master. the devices that are controlled by the master are called slaves. each byte is followed by one acknowledge bit. this acknowledge bit is a high level, put on the bus by the transmitter. the master generates an extra acknowledge related clock pulse. the slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte.
philips semiconductors pcf85103c-2 256 8-bit cmos eeprom with i 2 c-bus interface product data rev. 01 09 may 2002 7 of 20 9397 750 09646 ? koninklijke philips electronics n.v. 2002. all rights reserved. the master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. set-up and hold times must be taken into account. a master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master generation of the stop condition. 8.1.3 device addressing following a start condition, the bus master must output the address of the slave it is accessing. the address of the pcf85103c-2 is shown in figure 4 . to conserve power, no internal pull-up resistors are incorporated on the hardware selectable pins and they must be connected to either v dd or v ss . the last bit of the slave address de?nes the operation to be performed. when set to logic 1, a read operation is selected, while a logic 0 selects a write operation. 8.1.4 write operations byte/word write: for a write operation, the pcf85103c-2 requires a second address ?eld. this address ?eld is a word address providing access to the 256 words of memory. upon receipt of the word address, the pcf85103c-2 responds with an acknowledge and awaits the next eight bits of data, again responding with an acknowledge. word address is automatically incremented. the master can now terminate the transfer by generating a stop condition or transmit up to six more bytes of data and then terminate by generating a stop condition. after this stop condition, the e/w cycle starts and the bus is free for another transmission. its duration is 10 ms per byte. during the e/w cycle the slave receiver does not send an acknowledge bit if addressed via the i 2 c-bus. fig 4. slave address. 002aaa253 0010a2a1a0r/w fixed hardware selectable
philips semiconductors pcf85103c-2 256 8-bit cmos eeprom with i 2 c-bus interface product data rev. 01 09 may 2002 8 of 20 9397 750 09646 ? koninklijke philips electronics n.v. 2002. all rights reserved. page write: the pcf85103c-2 is capable of an eight-byte page write operation. it is initiated in the same manner as the byte write operation. the master can transit eight data bytes within one transmission. after receipt of each byte, the pcf85103c-2 will respond with an acknowledge. the typical e/w time in this mode is 9 3.5 ms = 31.5 ms. erasing a block of 8 bytes in page mode takes typical 3.5 ms and sequential writing of these 8 bytes another typical 28 ms. after the receipt of each data byte, the three low-order bits of the word address are internally incremented. the high-order ?ve bits of the address remain unchanged. the slave acknowledges the reception of each data byte with an ack. the i 2 c-bus data transfer is terminated by the master after the 8th byte with a stop condition. if the master transmits more than eight bytes prior to generating the stop condition, no acknowledge will be given on the ninth (and following) data bytes and the whole transmission will be ignored and no programming will be done. as in the byte write operation, all inputs are disabled until completion of the internal write cycles. fig 5. auto-increment memory word address; two byte write. s 0a slave address word address aa data p acknowledge from slave acknowledge from slave acknowledge from slave acknowledge from slave a data r/w auto increment word address auto increment word address mba701 fig 6. page write operation; eight bytes. s0a slave address word address a a data n acknowledge from slave acknowledge from slave acknowledge from slave r/w auto increment word address acknowledge from slave a data n + 1 auto increment word address 002aaa245 a acknowledge from slave a data n + 7 auto increment word address last byte
philips semiconductors pcf85103c-2 256 8-bit cmos eeprom with i 2 c-bus interface product data rev. 01 09 may 2002 9 of 20 9397 750 09646 ? koninklijke philips electronics n.v. 2002. all rights reserved. 8.1.5 read operations read operations are initiated in the same manner as write operations with the exception that the lsb of the slave address is set to logic 1. there are three basic read operations: current address read, random read, and sequential read. remark: the lower 8 bits of the word address are incremented after each transmission of a data byte (read or write). the msb of the word address, which is de?ned in the slave address, is not changed when the word address count over?ows. thus, the word address over?ows from 255 to 0, and from 511 to 256. fig 7. master reads pcf85103c-2 slave after setting word address (write word address; read data); sequential read. s0a slave address word address a a slave address acknowledge from slave acknowledge from slave acknowledge from slave r/w acknowledge from master a data auto increment word address mba703 p no acknowledge from master 1 data auto increment word address last byte r/w s1 n bytes at this moment master transmitter becomes master receiver and eeprom slave receiver becomes slave transmitter fig 8. master reads pcf85103c-2 immediately after ?rst byte (read mode); current address read. s 1a slave address data a1 data acknowledge from slave acknowledge from master no acknowledge from master r/w auto increment word address mba704 - 1 auto increment word address n bytes last bytes p
philips semiconductors pcf85103c-2 256 8-bit cmos eeprom with i 2 c-bus interface product data rev. 01 09 may 2002 10 of 20 9397 750 09646 ? koninklijke philips electronics n.v. 2002. all rights reserved. 9. limiting values 10. characteristics table 5: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage - 0.3 +6.5 v v i input voltage on any input pin | z i | > 500 w v ss - 0.8 +6.5 v i i input current on any input pin - 1 ma i o output current - 10 ma t stg storage temperature - 65 +150 c t amb operating ambient temperature - 40 +85 c table 6: characteristics v dd = 2.5 to 6.0 v; v ss =0v; t amb = - 40 to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supplies v dd supply voltage 2.5 - 6.0 v i ddr supply current read f scl = 100 khz v dd = 2.5 v - - 60 m a v dd = 6.0 v - - 200 m a i ddw supply current e/w f scl = 100 khz v dd = 2.5 v - - 0.6 ma v dd = 6.0 v - - 2.0 ma i dd(stb) standby supply current v dd = 2.5 v - - 3.5 m a v dd = 6.0 v - - 10 m a scl input (pin 6) v il low level input voltage - 0.8 - 0.3v dd v v ih high level input voltage 0.7v dd - +6.5 v i li input leakage current v i =v dd or v ss -- 1 m a f scl clock input frequency 0 - 100 khz c i input capacitance v i =v ss --7 pf sda input/output (pin 5) v il low level input voltage - 0.8 - 0.3v dd v v ih high level input voltage 0.7v dd - +6.5 v v ol low level output voltage i ol = 3 ma; v dd(min) - - 0.4 v i lo output leakage current v oh =v dd --1 m a c i input capacitance v i =v ss --7 pf data retention time t s data retention time t amb =55 c10 -- years
philips semiconductors pcf85103c-2 256 8-bit cmos eeprom with i 2 c-bus interface product data rev. 01 09 may 2002 11 of 20 9397 750 09646 ? koninklijke philips electronics n.v. 2002. all rights reserved. 11. i 2 c-bus characteristics [1] the hold time required (not greater than 300 ns) to bridge the unde?ned region of the falling edge of scl must be internally provided by a transmitter. table 7: i 2 c-bus characteristics all of the timing values are valid within the operating supply voltage and ambient temperature range and refer to v il and v ih with an input voltage swing from v ss to v dd ; see figure 9 . symbol parameter conditions min max unit f scl clock frequency 0 100 khz t buf bus free time between a stop and start condition 4.7 -m s t hd;sta start condition hold time after which ?rst clock pulse is generated 4.0 -m s t low low level clock period 4.7 -m s t high high level clock period 4.0 -m s t su;sta set-up time for start condition repeated start 4.7 -m s t hd;dat data hold time for bus compatible masters 5 -m s for bus devices [1] 0 - ns t su;dat data set-up time 250 - ns t r sda and scl rise time - 1 m s t f sda and scl fall time - 300 ns t su;sto set-up time for stop condition 4.0 -m s p = stop condition; s = start condition. fig 9. timing requirements for the i 2 c-bus. mba705 t buf hd;sta t scl sda p s t low t r hd;dat t su;dat t t f t high s hd;sta t su;sta t su;sto t p
philips semiconductors pcf85103c-2 256 8-bit cmos eeprom with i 2 c-bus interface product data rev. 01 09 may 2002 12 of 20 9397 750 09646 ? koninklijke philips electronics n.v. 2002. all rights reserved. 12. write cycle limits 13. external clock timing table 8: write cycle limits selection of the chip address is achieved by connecting the a0, a1 and a2 inputs to either v ss or v dd . symbol parameter conditions min typ max unit e/w cycle timing t e/w e/w cycle time internal oscillator - 7 - ms external clock 4 - 10 ms endurance n e/w e/w cycle per byte t amb = - 40 to +85 c 100000 -- cycles t amb =22 c 1000000 - cycles fig 10. one byte e/w cycle. t d t high f t r t low t stop 12 257 ptc sda scl mba697 fig 11. n bytes e/w cycle (n = 2 to 7). t d t high f t r t low t stop 12 ptc sda scl mba698 n x 256 + 1
philips semiconductors pcf85103c-2 256 8-bit cmos eeprom with i 2 c-bus interface product data rev. 01 09 may 2002 13 of 20 9397 750 09646 ? koninklijke philips electronics n.v. 2002. all rights reserved. fig 12. page mode. t d t high f t r t low t stop 12 ptc sda scl mba699 1153 (1) if an external clock is chosen, this information is latched internally by setting pin 7 (ptc) low after transmission of the eighth bits of the word address (negative edge of scl). thus the state of pin 7 may be previously unde?ned. leaving pin 7 low causes a higher standby current. (2) 1-byte programming. (3) 2-byte programming. (4) one page (8 bytes) programming. fig 13. external clock. s 0 a a data a data a p slave address word address (1) undefined 1 1 1 2 2 2 257 513 1153 clock (2) clock (3) clock (4) d t 0 negative edge scl 8-bit undefined low high ptc 2 i c-bus mba700
philips semiconductors pcf85103c-2 256 8-bit cmos eeprom with i 2 c-bus interface product data rev. 01 09 may 2002 14 of 20 9397 750 09646 ? koninklijke philips electronics n.v. 2002. all rights reserved. 14. package outline fig 14. dip8 package outline (sot97-1). references outline version european projection issue date iec jedec eiaj sot97-1 95-02-04 99-12-27 unit a max. 12 b 1 (1) (1) (1) b 2 cd e e m z h l mm dimensions (inch dimensions are derived from the original mm dimensions) a min. a max. b max. w m e e 1 1.73 1.14 0.53 0.38 0.36 0.23 9.8 9.2 6.48 6.20 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 1.15 4.2 0.51 3.2 inches 0.068 0.045 0.021 0.015 0.014 0.009 1.07 0.89 0.042 0.035 0.39 0.36 0.26 0.24 0.14 0.12 0.01 0.10 0.30 0.32 0.31 0.39 0.33 0.045 0.17 0.020 0.13 b 2 050g01 mo-001 sc-504-8 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 8 1 5 4 b e 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. pin 1 index dip8: plastic dual in-line package; 8 leads (300 mil) sot97-1
philips semiconductors pcf85103c-2 256 8-bit cmos eeprom with i 2 c-bus interface product data rev. 01 09 may 2002 15 of 20 9397 750 09646 ? koninklijke philips electronics n.v. 2002. all rights reserved. fig 15. so8 package outline (sot96-1). unit a max. a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 0.25 dimensions (inch dimensions are derived from the original mm dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.4 sot96-1 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 4 5 pin 1 index 1 8 y 076e03 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.20 0.19 0.16 0.15 0.050 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.01 0.041 0.004 0.039 0.016 0 2.5 5 mm scale so8: plastic small outline package; 8 leads; body width 3.9 mm sot96-1 97-05-22 99-12-27
philips semiconductors pcf85103c-2 256 8-bit cmos eeprom with i 2 c-bus interface product data rev. 01 09 may 2002 16 of 20 9397 750 09646 ? koninklijke philips electronics n.v. 2002. all rights reserved. 15. soldering 15.1 introduction this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 15.2 surface mount packages 15.2.1 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. 15.2.2 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end.
philips semiconductors pcf85103c-2 256 8-bit cmos eeprom with i 2 c-bus interface product data rev. 01 09 may 2002 17 of 20 9397 750 09646 ? koninklijke philips electronics n.v. 2002. all rights reserved. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 15.2.3 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 15.3 through-hole mount packages 15.3.1 soldering by dipping or by solder wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joints for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the speci?ed maximum storage temperature (t stg(max) ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 15.3.2 manual soldering apply the soldering iron (24 v or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds.
philips semiconductors pcf85103c-2 256 8-bit cmos eeprom with i 2 c-bus interface product data rev. 01 09 may 2002 18 of 20 9397 750 09646 ? koninklijke philips electronics n.v. 2002. all rights reserved. 15.4 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] for sdip packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 16. revision history table 9: suitability of ic packages for wave, re?ow and dipping soldering methods mounting package [1] soldering method wave re?ow [2] dipping through-hole mount dbs, dip, hdip, sdip, sil suitable [3] - suitable surface mount bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable - hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable - plcc [5] , so, soj suitable suitable - lqfp, qfp, tqfp not recommended [5][6] suitable - ssop, tssop, vso not recommended [7] suitable - table 10: revision history rev date cpcn description 01 20020509 product data; supersedes data in data sheet pcf85102c-2; pcf85103c-2 dated 2000 feb 15 (9397 750 06682). engineering change notice (ecn) 853-2342 28170 dated 2002 may 09. ? the format of this speci?cation has been redesigned to comply with philips semiconductors new presentation and information standard. ? figure 1 block diagram. modi?ed. ? figure 2 pin con?guration. modi?ed. ? figure 3 device addressing. added. ? figure 4 slave address. modi?ed. ? figure 6 page write operation; eight bytes. corrected.
9397 750 09646 philips semiconductors pcf85103c-2 256 8-bit cmos eeprom with i 2 c-bus interface ? koninklijke philips electronics n.v. 2002. all rights reserved. product data rev. 01 09 may 2002 19 of 20 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 17. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. 18. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 19. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 20. licenses data sheet status [1] product status [2] de?nition objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be publish ed at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a. purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c speci?cation de?ned by philips. this speci?cation can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2002. printed in the u.s.a all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 09 may 2002 document order number: 9397 750 09646 contents philips semiconductors pcf85103c-2 256 8-bit cmos eeprom with i 2 c-bus interface 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 device addressing . . . . . . . . . . . . . . . . . . . . . . . 4 8 functional description . . . . . . . . . . . . . . . . . . . 6 8.1 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . 6 8.1.1 bus conditions . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.1.2 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.1.3 device addressing . . . . . . . . . . . . . . . . . . . . . . 7 8.1.4 write operations . . . . . . . . . . . . . . . . . . . . . . . . 7 8.1.5 read operations . . . . . . . . . . . . . . . . . . . . . . . . 9 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10 11 i 2 c-bus characteristics . . . . . . . . . . . . . . . . . . 11 12 write cycle limits . . . . . . . . . . . . . . . . . . . . . . . 12 13 external clock timing . . . . . . . . . . . . . . . . . . . . 12 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 15 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 16 15.2 surface mount packages . . . . . . . . . . . . . . . . 16 15.2.1 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 16 15.2.2 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 16 15.2.3 manual soldering . . . . . . . . . . . . . . . . . . . . . . 17 15.3 through-hole mount packages . . . . . . . . . . . . 17 15.3.1 soldering by dipping or by solder wave . . . . . 17 15.3.2 manual soldering . . . . . . . . . . . . . . . . . . . . . . 17 15.4 package related soldering information . . . . . . 18 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 17 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19 18 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 20 licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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